The present invention relates to a ball-grid array (BGA) packaging technique and, more specifically, to the packaging technique of a ball-grid array (BGA) substrate having a heat sink layer. The heat sink layer can act as a ground plane or as a power plane or act as a both ground and power pattern plane, and thus shares the burden of the BGA pattern plane.
Following the advancement of manufacture of the integrated circuits (IC), it has become a trend to reduce the unit cost through diminution in the integral dimension of the die. The semiconductor manufacturers even expect that the performance of a certain aspects, such as processing speed can consequently gain remarkable improvements and that a single IC chip can encompass more functions. However, under the circumstances that the dimension of the die is diminished without lessening but adding the devices so as to increase the functions of the IC chips, it causes that the interconnects are inversely more intensive, and the accompanying increases in parasitical electric capacitance and electric resistance of the interconnects lead to degradation of the performance of the chips.
In order to solve the aforesaid problems, the semiconductor fabrication industry not only replaces the traditional aluminum conductive wires with copper conductive wires having a low electric resistance so as to reduce the electric resistance of conductive wires, but also gropes for dielectric layers with a low dielectric constant to resolve the issue of parasitical electric capacitance. Another factor with a direct and crucial effect on the cost and performance is the packaging technique, which can be understood because the I/O terminals will doubtless considerably increase in response to connection with the system when the IC chip devices step up to include new functions. And simultaneously the issues of the power consumption and heat dissipation of the IC chips are thus more prominent. Even such newly technology as the flip chip packaging technique and the ball-grid array (BGA) substrate packaging technique, also have to overcome the above-mentioned problems.
The steps of the conventional BGA substrate packaging process are described as follows:
Firstly, please refer to FIG. 1a, TAB sprocket holes 10 are punched in the sides of a substrate 5 which is pressed with a copper foil 8, and thus facilitate transportation of the substrate 5 on the conveying belt. The substrate 5 can be one of BT (bismaleimide-triazine), polyimide and enhanced epoxy resin etc. with/without glass fiber reinforced insulating substrates. For T-BGA, there is typically only one layer of a metal pattern on the substrate and the copper foil 8 is used to define a conductive trace and a pattern for connecting solder balls.
Then, as shown in FIG. 1b, the surface of the TAB sprocket holes 10 is desmeared and chemically polished, etc. Subsequently, a photo resist (not shown) is coated on the copper foil 8 and the copper foil 8 is processed with the photolithography procedures in order to define the pattern. After developed, the copper foil 8 is etched by using a photo resist pattern as the etching mask so as to form a conductive pattern and/or a pattern for connecting solder balls 20. Lastly, the photo resist is stripped.
Afterwards, as shown in FIG. 1c, a tape film 25 is covered on the backside of the substrate 5 opposite to the copper foil 8 so as to prevent the substrate from staining a solder mask. A layer of the solder mask 30, which is insulating is subsequently coated on the copper foil 8. The solder mask on the pattern 20 for connecting solder balls of the copper foil 8 is then removed through the photolithography procedures and the developing step.
Referring to FIG. 1d, the electroplating procedure subsequently proceeds so as to form in turn a nickel film layer and a gold film layer 35 on the copper foil 8. The tape film 25 is then immediately removed.
Please refer to FIG. 1e, the substrate is slit, and then an adhesive layer 42 is stuck to the backside of the substrate 5. The material in the central region of the substrate is cut off to form a cavity 40 for receiving the chip. If necessary, bus line through holes and device through holes are punched. Then, another copper foil 55 is stuck onto the adhesive layer 42 to make a heat sink layer and to support the BGA substrate. Finally, solder balls 45 are formed on the gold film layer 35. The result is as shown in FIG. 1f. 
In the traditional process, it needs to stick the heat sinks piece by piece onto the adhesive layer 42 in order to form the heat sink layer. In this connection, it is time-consuming and the effect of heat dissipation is also restricted due to the fact that the heat sink 55 is separated from the power rings or ground rings in the front surface of the pattern layer by the layer of the insulating substrate without connection with each other.
The technique as shown in FIG. 1g and FIG. 1h is employed by 3M company, which plates the TAB sprocket holes 10 by electroless plating after punching the TAB sprocket holes 10 so that the front surface of the substrate pattern can be connected with the heat sink layer. However, the above-mentioned partial connection is unable to sufficiently dissipate the heat of the pattern layer.
Therefore, the efficiency of the heat sink layer of the BGA substrate made by the prior art is not good. The present invention provides a new construction of the BGA substrate and the producing process thereof to improve the aforesaid problems.
The one objective of the present invention is to provide an improved structure of a ball-grid array package substrate and processes for producing thereof.
Another objective of the present invention is to connect the pattern layer of a BGA substrate with patterns for ground and for power of the heat sink layer through electrically and thermally conductive via holes which are plugged with conductive paste.
An improved structure of a ball-grid array package substrate is disclosed, wherein one side of the BGA substrate has a single pattern layer for connecting with solder balls as well as conductive lines, and a heat sink layer is bonded to the other side of the substrate. The heat sink layer is also a layer for ground so as to provide an additional dimension required by the pattern layer for ground patterns, where the ground solder balls of the substrate are connected with the heat sink layer through electrically and thermally conductive via holes plugged with conductive paste. Alternatively, the heat sink layer can also include only patterns for power so as to provide an additional dimension required by the BGA pattern layer for power patterns.
Furthermore, the heat sink layer can also include patterns both for ground and for power so as to provide an additional dimension required by the BGA pattern layer, and hence the heat sink layer has better electrical and thermal performances.
The process for producing the structure of the ball-grid array package substrate of this invention is that two sides of a substrate are respectively covered with one layer of a release film, and then the substrate is drilled and slit to form a plurality of via holes and a cavity, wherein the via holes are located in predetermined positions of solder balls for ground or for power of the substrate, and the cavity is located for receiving a chip. Afterwards, the via holes of the substrate are plugged with conductive paste.
In a first embodiment of the present invention, one layer of the release film is subsequently removed from one side of the substrate to laminate a heat sink layer thereon, and then a layer of black oxide is formed onto the surface of the heat sink layer within the cavity. After the remaining layer of the release film is removed from the other side of the substrate, a copper foil is laminated thereon. Then, the copper foil is patterned by means of photolithography and etching technology to form a BGA pattern layer having patterns for connecting solder balls and conductive traces. Black ink is coated on the surface of the heat sink layer for insulating, and a solder mask is coated on the pattern layer. Subsequently, another photolithography procedure is performed to bare portions of the pattern layer where the solder balls are connected. An electroplating or electroless plating process is performed to plate in turn a Ni film and an Au film on the uncovered portions of the pattern layer, and then the solder balls are mounted onto the Au film of the pattern layer. Finally, the chip is set onto the layer of black oxide in the cavity, and bonding pads of the chip are connected with the pattern layer by wire bonding, and then a resin is filled in the cavity to fix the chip and the wires.
In a second embodiment of the present invention, after the via holes of the substrate are plugged with conductive paste in the first embodiment, the two layers of the release films are removed. Then, a copper foil and a heat sink layer are laminated onto the substrate. Next, the copper foil is patterned by photolithography and etching technology to form a BGA pattern layer. Subsequently, a protective film is stick onto the BGA pattern layer. After a layer of black oxide is formed onto the surface of the heat sink layer within the cavity, the protective film is removed. The other subsequent steps are the same as described in the first embodiment.
The steps of the process for producing the structure of the ball-grid array package substrate of which the heat sink layer has patterns both for ground and for power, i.e. a third embodiment of this invention, are that two sides of a substrate having a layer of copper foil on one side thereof are respectively covered with one layer of a release film. The substrate is then drilled and slit to form a plurality of via holes and a cavity therein, wherein the via holes are located in predetermined positions of ball-grid for ground and of ball-grid for power of the substrate, and the cavity is located for receiving a chip. Next, the via holes of the substrate are plugged with conductive paste. The release films are removed and a heat sink layer is laminated on the other side of the substrate. The copper foil and the heat sink layer of the substrate are respectively covered with a protection film, and then a layer of black oxide is formed onto the surface of the heat sink layer within the cavity.
After the protection films are removed, the copper foil is patterned by means of photolithography and etching technology to form a BGA pattern layer having signal patterns, conductive traces and patterns for connecting power solder balls and ground solder balls. Moreover, the heat sink layer is also patterned to form therein patterns for power and for ground. Later, black ink is coated on the surface of the heat sink layer for protection, and a solder mask is coated on the pattern layer. Subsequently, another photolithography procedure is performed to bare portions of the pattern layer where the solder balls are connected. An electroplating or electroless plating process is performed to plate in turn a Ni film and an Au film on the uncovered portions of the pattern layer, and then the solder balls are mounted onto the Au film of the pattern layer. Finally, the chip is set onto the layer of black oxide in the cavity, and bonding pads of the chip are connected with the pattern layer by wire bonding, and then a resin is filled in the cavity to fix the chip and the wires.